This application claims benefit of priority under 35 U.S.C. xc2xa7119 to Japanese Patent Application No. 2002-272022, filed on Sep. 18, 2002, the entire contents of which are incorporated by reference herein.
1. Field of the Invention
The present invention relates to a semiconductor memory device and a method of controlling the same, and particularly relates to an FBC (Floating Body Cell) structured semiconductor memory device and a method of controlling the same.
2. Related Background Art
An FBC memory is a volatile memory which can be formed on an SOI substrate and expected as a semiconductor memory device which replaces DRAMs. The FBC memory has an advantage of being suitable for high-density integration because of its small cell size. The basic explanation of this FBC memory is disclosed, for example, in document 1 (T. Ohsawa et al., xe2x80x9cMemory Design Using One-Transistor Gain Cell on SOIxe2x80x9d, ISSCC Digest of Technical Papers, pp152-153, 2002).
FIG. 30 is a plane layout of a memory cell array portion of the FBC memory, FIG. 31 is a sectional view taken along the line A-Axe2x80x2 of the memory cell array in FIG. 30, FIG. 32 is a sectional view taken along the line B-Bxe2x80x2 of the memory cell array in FIG. 30, and FIG. 33 is a sectional view taken along the line C-Cxe2x80x2 of the memory cell array in FIG. 30. FIG. 34 is a circuit diagram showing an equivalent circuit of this memory cell array.
As can be seen from these drawings, the FBC memory uses MIS transistors (Metal-Insulator-Semiconductor transistors) arranged in a matrix form on the SOI substrate as memory cells MC. In an example shown in these drawings, the SOI substrate includes an N+-type diffusion layer 12 formed on a P-type semiconductor substrate 10 and an insulating film (a silicon oxide film, for example) 14 formed on the diffusion layer 12. Moreover, this memory cell array includes a plurality of word lines WL extending in a first direction, a plurality of source lines SL extending also in the first direction, and a plurality of bit lines BL extending in a second direction which intersects the first direction.
A drain 20 of the memory cell MC is connected to the bit line BL via a bit line contact 21, a source 22 is connected to the source line SL, and a gate electrode 24 constitutes the word line WL. A portion between the drain 20 and the source 22 is electrically in a floating state and forms a channel body 28. The aforementioned gate electrode 24 is located above this channel body 28 with a gate insulating film 26 therebetween. The source line SL is always fixed to 0 V.
The drain 20 and the source 22 of the memory cell MC are formed by an N-type semiconductor layer, and the channel body 28 is formed by a P-type semiconductor layer. The memory cell MC stores data depending on whether or not holes which are majority carriers are accumulated. Hereafter, a state in which holes are accumulated in the channel body 28 is defined as xe2x80x9c1xe2x80x9d and a state in which holes are not accumulated therein is defined as xe2x80x9c0xe2x80x9d.
N+-type polysilicon pillars 30 shown in FIG. 32 and FIG. 33 are each an electrode formed to maintain the accumulation state of holes. Namely, the polysilicon pillar 30 and the channel body 28 form capacitance, and by applying negative voltage to the polysilicon pillar 30, the accumulation state of holes can be maintained for a longer time. However, the holes accumulated in the channel body 28 come off the channel body 28 after a lapse of a sufficiently long time because of leakage from a PN junction portion which exists in the drain 20 and the source 22. Therefore, it is necessary to execute a data refresh in the FBC memory likewise with the DRAM.
Next, the operational principle of the FBC structured memory cell MC will be explained. When data xe2x80x9c1xe2x80x9d is written into the FBC structured memory cell MC, as shown in FIG. 35, for example, 1.5 V is applied to the word line WL and 1.5 V is applied to the bit line BL. Since a transistor composing the memory cell MC operates in a saturation region, holes are generated by impact ionization. The generated holes move to the lower side of the channel body 28 and they are accumulated in the capacitance.
When data xe2x80x9c0xe2x80x9d is written, as shown in FIG. 36, for example, 1.5 V is applied to the word line WL and xe2x88x921 V is applied to the bit line BL. Thereby, the PN junction of the drain 20 is forward biased, and holes are emitted to the bit line BL.
When data is read, as shown in FIG. 37, for example, 1.5 V is applied to the word line WL, 0.2 V is applied to the bit line BL, and the transistor composing the memory cell MC is turned on. Thresholds of the transistor when holes are accumulated in the channel body 28 and when holes are not accumulated therein are different because of a back bias effect. Accordingly,as shown in FIG. 38, the current characteristic of the transistor varies according to data. By detecting this difference in current, data can be read. Since the voltage of the bit line BL is low when data is read, the transistor of the memory cell MC operates in a linear region. Hence, impact ionization does not occur. Consequently, holes are not generated, and data in the memory cell MC is not destroyed. Namely, in the FBC structured memory cell MC, non-destructive read-out of data is possible.
Note that, in the non-selected memory cell MC in the memory cell array, xe2x88x921.5 V is applied to the word line WL and 0 V is applied to the bit line BL.
Next, the entire configuration of a semiconductor memory device is explained which uses the memory cell array of the FBC memory. FIG. 39 is a layout showing the configuration of such a semiconductor memory device. The FBC memory aims at replacing the DRAM, and therefore, similarly to the DRAM, it performs address signal multiplexing by a /RAS signal and a /CAS signal. An art regarding this address signal multiplexing is disclosed, for example, in document 2 (Kiyoo Itoh, xe2x80x9cVLSI Memoryxe2x80x9d, Baifukan, p97, 1995).
As shown in FIG. 39, a memory cell array 100 includes the memory cells MC with the aforementioned configuration, a row decoder 102 is provided on one end side in a word line WL direction thereof, and a bit line selector 104 is provided on one end side in a bit line BL direction thereof.
An address signal inputted from an ADDRESS terminal is inputted to a row address buffer 110 and a column address buffer 112. The row address buffer 110 sends out the inputted address signal (which is a row address signal) to a predecoder 120 based on the /RAS signal, and the row address signal is inputted to the row decoder 102 via the predecoder 120. The row decoder 102 selects the word line WL based on the row address signal.
Meanwhile, the column address buffer 112 sends out the inputted address signal (which is a column address signal) to the bit line selector 104 based on the /CAS signal. The bit line selector 104 selects the bit line BL based on the column address signal, and connects the selected bit line BL to a sense unit 130.
Program data is inputted from a DIN pad to this semiconductor memory device and sent out to the sense unit 130 via a data input buffer 140. On the other hand, read data sensed in the sense unit 130 is outputted to the outside of this semiconductor memory device from a DOUT pad via a data output buffer 150 and an off-chip driver 152. Inside the semiconductor memory device,in addition to these, a controller 160 for generating various control signals and a voltage generating circuit 162 for generating various internal voltages are provided.
A plurality of sense units 130 are connected to the bit line selector 104. FIG. 40 is a diagram showing a circuit configuration of one sense unit 130 and circuit configurations of its related circuits. As shown in FIG. 40, the one sense unit 130 includes a sense amplifier 200, a latch circuit 202, and an MIS transistor Tr200.
The sense amplifier 200 detects a cell current read from the memory cell MC by monitoring a current flowing through the bit line BL, and outputs xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d data depending on the value of the cell current. When a control signal SAEN is high, the sense amplifier 200 is activated and brought into an enable state.
The latch circuit 202 includes two inverters IN200 and IN202. A logic symbol with a square inversion symbol is 1.5 V at a high level and xe2x88x921 V at a low level. This is also applied to the following explanations.
The sense unit 130 is connected to one bit line BL via the bit line selector 104. An MIS transistor Tr202 for reset is provided in each bit line BL. A BLRST signal is high except during a read sequence, a write sequence, and a refresh sequence, and the bit line BL is grounded at 0 V via the MIS transistor Tr202.
A data input line D connected to the data input buffer 140 is connected to the latch circuit 202 via an MIS transistor Tr210 and the MIS transistor Tr200. Hence, when a WCSL signal and an SAON signal go high, these MIS transistor Tr210 and the MIS transistor Tr200 are turned on, and data in the data input line D can be captured by the latch circuit 202.
A data output line Q connected to the data output buffer 150 is connected to an output terminal of the inverter IN202 in the latch circuit 202 via an MIS transistor Tr220 and an MIS transistor Tr222, and similarly a data output line /Q connected to the data output buffer 150 is connected to an output terminal of the inverter IN200 in the latch circuit 202 via an MIS transistor Tr230 and an MIS transistor Tr232. Hence, it becomes possible to send out data latched by the latch circuit 202 to the data output lines Q and /Q when an RCS signal goes high.
Next, operational waveforms in the read sequence, the write sequence, and the refresh sequence in the aforementioned semiconductor memory device will be explained briefly. FIG. 41 is a diagram showing operational waveforms in the read sequence, FIG. 42 is a diagram showing operational waveforms in the write sequence, and FIG. 43 is a diagram showing operational waveforms in the refresh sequence.
As shown in FIG. 41, in the read sequence, after data sensed by the sense amplifier 200 is inputted to the latch circuit 202, the RCS signal goes high, and data which has been read is transferred to the data output buffer 150 via the data output lines Q and /Q. Note that, when an LTC signal inputted to the latch circuit 202 is high, this latch circuit 202 is in a data capture state, and when the LTC signal is low, the latch circuit 202 is in a hold state.
As shown in FIG. 42, in the write sequence, program data is inputted to the latch circuit 202, the program data is then sent out to the bit line BL, and a write into the memory cell MC is performed.
As shown in FIG. 43, in the refresh operation, data in the memory cell MC is read by the sense amplifier 200 and latched by the latch circuit 202. Subsequently,the latched data is written again into the memory cell MC. The memory cell MC to be refreshed is selected based on a refresh address signal generated by the controller 160. This refresh address signal includes a row address signal and a column address signal. More specifically, the controller 160 selects one word line WL based on one row address signal, and refreshes all of the memory cells MC connected to this word line WL while incrementing the column address. Thereafter, it increments the row address signal and refreshes all of the memory cells MC connected to the next word line WL. Thus, the controller 160 performs control in such a manner that all of the memory cells are refreshed within a predetermined time interval.
The aforementioned FBC structured memory cell MC, however, has the following problems. Namely, as shown in FIG. 44, when the memory cell MC holding xe2x80x9c1xe2x80x9d data and the memory cell MC holding xe2x80x9c0xe2x80x9d data share the drain 20, a situation in which the memory cell MC holding the xe2x80x9c1xe2x80x9d data (hereinafter referred to as a selected cell) is selected and xe2x80x9c0xe2x80x9d data is written thereinto is assumed. In such a situation, holes accumulated in the selected cell are emitted to the bit line BL via the drain 20, but part of holes which are originally to be emitted to the bit line BL get into the channel body 28 of the adjacent memory cell MC (hereinafter referred to as an adjacent cell) through the drain 20. This is a phenomenon which occurs because the N-type drain 20 connected to the bit line BL and the P-type channel bodies 28 located on its both sides compose a PNP bipolar transistor. Such a phenomenon is hereinafter called xe2x80x9c0xe2x80x9d disturb.
Most of holes which come off the selected cell are emitted to the bit line BL or recombined to electrons in the N-type drain 20, and thus it can be said that the percentage of holes which get into the channel body 28 of the adjacent cell is low. Accordingly, data in the adjacent cell does not change from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d by a single xe2x80x9c0xe2x80x9d disturb. However, if the xe2x80x9c1xe2x80x9d data and the xe2x80x9c0xe2x80x9d data are alternately written into the selected cell, and this xe2x80x9c0xe2x80x9d disturb repeatedly occurs, the data in the adjacent cell is changed from xe2x80x9c0xe2x80x9d to xe2x80x9c1xe2x80x9d.
In the FBC structured memory cell MC, there is another disturb. As shown in FIG. 45, a case where the xe2x80x9c1xe2x80x9d data is written into the selected cell is assumed. It is supposed that the adjacent cell which shares the source 22 with the selected cell holds the xe2x80x9c0xe2x80x9d data. Holes are continuously generated by impact ionization while the xe2x80x9c1xe2x80x9d data is written into the selected cell, but there is a limit to the quantity of holes to be accumulated in the channel body 28. Hence, if the state in which the xe2x80x9c1xe2x80x9d data is written into the selected cell continues for a long time, excess holes are emitted to the source 22. Part of holes flowing into the source 22 further flow into the channel body 28 of the adjacent cell. Such a phenomenon is hereinafter called xe2x80x9c1xe2x80x9d disturb.
If this xe2x80x9c1xe2x80x9d disturb is repeated, the data in the adjacent cell is destroyed. This xe2x80x9c1xe2x80x9d disturb occurs even when the selected cell before write operation holds the xe2x80x9c1xe2x80x9d data and even when it holds the xe2x80x9c0xe2x80x9d data.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a semiconductor memory device comprises:
a memory cell array which includes a plurality of memory cells arranged in a matrix form, each of the memory cells including a transistor which has a source, a drain and a channel body between the source and the drain, each of the memory cells storing data depending on whether or not majority carriers are accumulated in the channel body;
a plurality of word lines, each of which is connected to gate electrodes of the memory cells arranged in a first direction;
a plurality of bit lines, each of which is connected to the memory cells arranged in a second direction which intersects the first direction and configured to read data stored in the memory cells;
a decoding circuit which is supplied with an address signal and a first control signal, the decoding circuit driving a selected word line which is the word line specified by the address signal or an adjacent word line which is the word line adjacent to the selected word line on the basis of the first control signal; and
a sense unit which is connected to a bit line and reads data stored in the memory cell which is connected to the word line driven by the decoding circuit.
According to another aspect of the present invention, a method of controlling a semiconductor memory device includes:
a memory cell array which includes a plurality of memory cells arranged in a matrix form, each of the memory cells including a transistor which has a source, a drain and a channel body between the source and the drain, each of the memory cells storing data depending on whether or not majority carriers are accumulated in the channel body;
a plurality of word lines, each of which is connected to gate electrodes of the memory cells arranged in a first direction; and
a plurality of bit lines, each of which is connected to the memory cells arranged in a second direction which intersects the first direction and configured to read data stored in the memory cells, and
the method comprises:
acquiring an address signal;
acquiring a first control signal;
driving a selected word line which is the word line specified by the address signal or an adjacent word line which is the word line adjacent to the selected word line on the basis of the first control signal; and
reading data stored in the memory cell which is connected to the driven word line, via the bit line.